# DRC in real time **URL:** \ **Category:** Improvement Ideas\ **Created:** [December 30, 2019, 9:40pm UTC](https://librepcb.discourse.group/t/drc-in-real-time/170 "2019-12-30T21:40:34Z")\ **Posts on this page:** 3\ **Page:** 1
**Author:** ![spkdd](https://avatars.discourse-cdn.com/v4/letter/s/e19b73/32.png) [@spkdd](https://librepcb.discourse.group/u/spkdd)\ **Post date:** [December 30, 2019, 9:40pm UTC](https://librepcb.discourse.group/t/drc-in-real-time/170/1 "2019-12-30T21:40:34Z")
Is the DRC (board editor) doing its job in real time as we work on it? Or is it only triggered manually just like it’s done in eagle? I think it would be better if it was doing it as we are working, so we get a warning as soon as we caused something violating DRC. ---
**Author:** ![dbrgn](https://yyz2.discourse-cdn.com/free1/user_avatar/librepcb.discourse.group/dbrgn/32/25_2.png) [@dbrgn](https://librepcb.discourse.group/u/dbrgn)\ **Post date:** [January 2, 2020, 2:43pm UTC](https://librepcb.discourse.group/t/drc-in-real-time/170/2 "2020-01-02T14:43:55Z")
Check out the release notes of the 0.1.3 release: [https://librepcb.org/blog/2019-11-30\_release\_0.1.3/](https://librepcb.org/blog/2019-11-30_release_0.1.3/) The DRC is not (yet?) working in real-time, you have to run it manually. Furthermore, design rule options are not yet saved to files, so you have to re-enter them after opening the project the next time. This will be implemented in the next major release of LibrePCB (because it requires a file format change). ---
**Author:** ![spkdd](https://avatars.discourse-cdn.com/v4/letter/s/e19b73/32.png) [@spkdd](https://librepcb.discourse.group/u/spkdd)\ **Post date:** [January 2, 2020, 2:49pm UTC](https://librepcb.discourse.group/t/drc-in-real-time/170/3 "2020-01-02T14:49:29Z")
Alright. That’s one area where eagle can be easily beat. And while at it, I don’t think making tented vias should be done via a trick like it’s done with eagle. There has to be a more explicit way and per via.