# Errors while generating schematic **URL:** \ **Category:** Help\ **Created:** [May 2, 2023, 3:22pm UTC](https://librepcb.discourse.group/t/errors-while-generating-schematic/535 "2023-05-02T15:22:18Z")\ **Posts on this page:** 17\ **Page:** 1
**Author:** ![kapila](https://avatars.discourse-cdn.com/v4/letter/k/73ab20/32.png) [@kapila](https://librepcb.discourse.group/u/kapila)\ **Post date:** [May 2, 2023, 3:22pm UTC](https://librepcb.discourse.group/t/errors-while-generating-schematic/535/1 "2023-05-02T15:22:18Z")
I am learning the tool through documentation. I could generate a component for Max 20087 led driver. But while using in schematic many circuit errors. I am getting many ‘unconnected component signal: “1” from “L1”.’ Any clue? ---
**Author:** ![ubruhin](https://avatars.discourse-cdn.com/v4/letter/u/c89c15/32.png) [@ubruhin](https://librepcb.discourse.group/u/ubruhin)\ **Post date:** [May 2, 2023, 3:37pm UTC](https://librepcb.discourse.group/t/errors-while-generating-schematic/535/2 "2023-05-02T15:37:21Z")
Hi! Sounds like you simply did not connect any wire to pin 1 of L1 - in that case, the error just says it makes no sense to leave this pin unconnected. The error should disappear after you connect a wire. If this doesn’t help, please post a screenshot which shows the problem. ---
**Author:** ![kapila](https://avatars.discourse-cdn.com/v4/letter/k/73ab20/32.png) [@kapila](https://librepcb.discourse.group/u/kapila)\ **Post date:** [May 2, 2023, 3:59pm UTC](https://librepcb.discourse.group/t/errors-while-generating-schematic/535/3 "2023-05-02T15:59:33Z")
Thanks for your quick response. In fact wire is connected and is visible in schematic. But there is no option to attach as PDF schematic . Regards, Kapila ---
**Author:** ![ubruhin](https://avatars.discourse-cdn.com/v4/letter/u/c89c15/32.png) [@ubruhin](https://librepcb.discourse.group/u/ubruhin)\ **Post date:** [May 2, 2023, 4:07pm UTC](https://librepcb.discourse.group/t/errors-while-generating-schematic/535/4 "2023-05-02T16:07:49Z")
> [@kapila](#): > > But there is no option to attach as PDF schematic . I’m not sure about PDF but at least PNG screenshot should be possible to attach here. Note that another possible reason for your problem might be in the library component. Make sure to connect symbol pins to component signals as described [here](https://librepcb.org/docs/quickstart/create-library-elements/component/#connect-pins-to-signals). To modify this table, open your component in the library editor and double-click on the symbol variant (usually called “default”). Then a dialog opens with this pin-to-signal mapping table. If you’re not sure if it is correct, just post a screenshot of that table as well. ---
**Author:** ![kapila](https://avatars.discourse-cdn.com/v4/letter/k/73ab20/32.png) [@kapila](https://librepcb.discourse.group/u/kapila)\ **Post date:** [May 2, 2023, 4:13pm UTC](https://librepcb.discourse.group/t/errors-while-generating-schematic/535/5 "2023-05-02T16:13:48Z")
Thank you. This could be a problem while generating component. I will try. Regards, Kapila ---
**Author:** ![kapila](https://avatars.discourse-cdn.com/v4/letter/k/73ab20/32.png) [@kapila](https://librepcb.discourse.group/u/kapila)\ **Post date:** [May 3, 2023, 4:20pm UTC](https://librepcb.discourse.group/t/errors-while-generating-schematic/535/6 "2023-05-03T16:20:17Z")
Hi Ubruhin Thanks a lot for guiding me. I have made a mistake of not connecting signals to pin in component configuration. Can I delete the saved component as it has some dependencies for device? If I make new what about the existing component in the saved work space folder? Please advise. Regards, Kapila ---
**Author:** ![ubruhin](https://avatars.discourse-cdn.com/v4/letter/u/c89c15/32.png) [@ubruhin](https://librepcb.discourse.group/u/ubruhin)\ **Post date:** [May 5, 2023, 11:45am UTC](https://librepcb.discourse.group/t/errors-while-generating-schematic/535/7 "2023-05-05T11:45:47Z")
Hi @kapila, Sorry for the late response. You can delete the component if you like, but then you either need to adjust or delete dependent devices too. But you could also proceed without deleting the component: - Fix the mistake in the existing component and save it to disk - With each device depending on that component: - Open the device in the library editor - Select some other component (to break up existing connections) - Select the correct component again (the one selected before) - Re-assign the pad-to-signal connections - Save to disk - With each project using the corrected component: - Remove all instances of that component from the schematic - Re-add the component (with the component chooser dialog) - Re-create the connections (wires, traces, …) ---
**Author:** ![kapila](https://avatars.discourse-cdn.com/v4/letter/k/73ab20/32.png) [@kapila](https://librepcb.discourse.group/u/kapila)\ **Post date:** [May 7, 2023, 5:56am UTC](https://librepcb.discourse.group/t/errors-while-generating-schematic/535/8 "2023-05-07T05:56:58Z")
Hi Ubruhin, Very many thanks. I am just learning the tool. I am learning by making mistakes. The tool seems to be very versatile and structured and easy to locate the component and package. I will try to master all commands. ---
**Author:** ![kapila](https://avatars.discourse-cdn.com/v4/letter/k/73ab20/32.png) [@kapila](https://librepcb.discourse.group/u/kapila)\ **Post date:** [May 9, 2023, 5:36am UTC](https://librepcb.discourse.group/t/errors-while-generating-schematic/535/9 "2023-05-09T05:36:16Z")
Hi Ubruhin, I am planning to create a TSSOP16 package as per the attached file. I have created the package as per the data sheet. Why many warnings for 0.15mm clearance and in which direction? I presume these warnings are for land pattern designs not for package images. Pl clarify for me. Regards, Kanakaraju Kapila ![Screenshot from 2023-05-09 11-04-07.png](https://global.discourse-cdn.com/free1/uploads/librepcb1/original/1X/fed4c1a5e830b17a7dcd96aec654b631acfac6f7.png) ![Screenshot from 2023-05-09 11-00-14.png](https://global.discourse-cdn.com/free1/uploads/librepcb1/original/1X/d6d9f4492a29b5d556172ff1b6d83ba9c1e145e0.png) ---
**Author:** ![ubruhin](https://avatars.discourse-cdn.com/v4/letter/u/c89c15/32.png) [@ubruhin](https://librepcb.discourse.group/u/ubruhin)\ **Post date:** [May 9, 2023, 11:37am UTC](https://librepcb.discourse.group/t/errors-while-generating-schematic/535/10 "2023-05-09T11:37:07Z")
> [@kapila](#): > > Why many warnings for 0.15mm clearance and in which direction? If you click on the `?` button of the message, LibrePCB explains very clearly why this warning appears, or what’s not clear about it? Please also check out our library conventions which explain [how to use the placement layer](https://librepcb.org/docs/library-conventions/packages/#placement-layer). You could also take a look at our official footprints to see how we draw the outlines without raising this warning. ---
**Author:** ![kapila](https://avatars.discourse-cdn.com/v4/letter/k/73ab20/32.png) [@kapila](https://librepcb.discourse.group/u/kapila)\ **Post date:** [May 9, 2023, 3:33pm UTC](https://librepcb.discourse.group/t/errors-while-generating-schematic/535/11 "2023-05-09T15:33:13Z")
Hi Ubruhin, Thanks a lot for your guidance. I still need more clarity. In generating package we are designing two dimensional package view which is as per the manufacturer standard TSSOP16 and not land pattern on PCB. Am I correct? Regards, Kapila ---
**Author:** ![ubruhin](https://avatars.discourse-cdn.com/v4/letter/u/c89c15/32.png) [@ubruhin](https://librepcb.discourse.group/u/ubruhin)\ **Post date:** [May 9, 2023, 4:17pm UTC](https://librepcb.discourse.group/t/errors-while-generating-schematic/535/12 "2023-05-09T16:17:01Z")
Hi, Sorry I don’t understand your question. The library element is called _package_ but what you’re drawing inside the editor is the _footprint_, i.e. the 2D land pattern. And the _placement_ layer is **not** intended for any object which is visible in your datasheet – it is intended for placement help which will be contained on the silkscreen (for example a pin-1 marking). Since silkscreen cannot be printed on copper pads, a minimum clearance is required/recommended. The body outline as shown in the datasheet shall be drawn on the _top documentation_ layer. But that’s all described in more detail in the [library conventions](https://librepcb.org/docs/library-conventions/packages/#documentation-layer). If this doesn’t answer your question, please explain your question in more detail. ---
**Author:** ![kapila](https://avatars.discourse-cdn.com/v4/letter/k/73ab20/32.png) [@kapila](https://librepcb.discourse.group/u/kapila)\ **Post date:** [May 10, 2023, 4:34am UTC](https://librepcb.discourse.group/t/errors-while-generating-schematic/535/13 "2023-05-10T04:34:41Z")
Hi Ubruhin, Yes now I understand the tool is used to design land pattern for the TSSOP package. Going forward I want to design a PCB layout for a smd LED of CREE. I want to superimpose a secondary optics from LEDIL on the LED. I feel librepcb can help me. Very many thanks Regards, Kapila ---
**Author:** ![kapila](https://avatars.discourse-cdn.com/v4/letter/k/73ab20/32.png) [@kapila](https://librepcb.discourse.group/u/kapila)\ **Post date:** [May 19, 2023, 3:42pm UTC](https://librepcb.discourse.group/t/errors-while-generating-schematic/535/14 "2023-05-19T15:42:47Z")
Hi Ubruhin, I have created schematic for LED driver.(screen shot attached). I am having trouble to generate the BOM. There is no library for inductor of coilcraft. I have generated my library after creating schematic. I am not being able to include in the BOM. (screen shot of BOM). Please help the methodology. ![image](https://global.discourse-cdn.com/free1/uploads/librepcb1/original/1X/85e44fcec866edb76943630c5070b001f2b1389f.png) file:///home/kanakaraju/Pictures/Screenshots/Screenshot%20from%202023-05-19%2020-45-53.png Thanks and regards Kapila ---
**Author:** ![kapila](https://avatars.discourse-cdn.com/v4/letter/k/73ab20/32.png) [@kapila](https://librepcb.discourse.group/u/kapila)\ **Post date:** [May 19, 2023, 3:54pm UTC](https://librepcb.discourse.group/t/errors-while-generating-schematic/535/15 "2023-05-19T15:54:01Z")
![Screenshot from 2023-05-19 20-45-53](https://global.discourse-cdn.com/free1/uploads/librepcb1/original/1X/0c515cbd1de1979c3c81f556e9e99a13de96f23b.png) ---
**Author:** ![ubruhin](https://avatars.discourse-cdn.com/v4/letter/u/c89c15/32.png) [@ubruhin](https://librepcb.discourse.group/u/ubruhin)\ **Post date:** [May 22, 2023, 2:05pm UTC](https://librepcb.discourse.group/t/errors-while-generating-schematic/535/16 "2023-05-22T14:05:56Z")
Hi, If you mean L1: It is in the BOM, but without value. Double-click on the inductor in the schematic and set a value. Then it should be listed as a separate row in the BOM. ---
**Author:** ![kapila](https://avatars.discourse-cdn.com/v4/letter/k/73ab20/32.png) [@kapila](https://librepcb.discourse.group/u/kapila)\ **Post date:** [May 24, 2023, 4:02am UTC](https://librepcb.discourse.group/t/errors-while-generating-schematic/535/17 "2023-05-24T04:02:10Z")
Hi Ubruhin, Great. Thank you. Regards, Kapila