Yes that is the way our file format works. But I agree with your initial comment that it’s not good to operate directly on our file format (as it is subject to change in future versions).
The proper way would be to use a netlist export instead, but unfortunately there doesn’t exist a standard file format for netlist. Every tool uses something different.
Actually I am thinking about the following way: We currently already have a JSON project export, which is intended to provide a stable, well-defined way to extract data from a LibrePCB project. Currently it contains mainly information about the PCB (dimension, design rules, used drill sizes, …). But it could be extended to also contain netlist information. For example something like this:
{
"library": {
"components": {
"ef80cd5e-2689-47ee-8888-31d04fc99174": {
"name": "Resistor",
"signals": {
"3452d36e-1ce8-4b7c-8e5b-90c2e4929ed8": {
"name": "1"
},
"ad623f98-9e73-49c3-9404-f7cfa99d17cd": {
"name": "2"
}
}
}
}
},
"nets": {
"1c52cd66-5f72-4e55-b973-c8db6accf092": {
"name": "GND"
}
},
"components": {
"56da425a-e5b9-4d4b-a579-b303d7755011": {
"name": "C1",
"value": "100nF",
"lib_component": "ef80cd5e-2689-47ee-8888-31d04fc99174",
"nets": {
"3452d36e-1ce8-4b7c-8e5b-90c2e4929ed8": "1c52cd66-5f72-4e55-b973-c8db6accf092",
"ad623f98-9e73-49c3-9404-f7cfa99d17cd": null
}
}
}
}
And then for the converter to DIYLC you may use a mapping from standard components to DIYLC components, like this:
{
"ef80cd5e-2689-47ee-8888-31d04fc99174": {
"type": "RESISTOR",
"pins": {
"3452d36e-1ce8-4b7c-8e5b-90c2e4929ed8": "1",
"ad623f98-9e73-49c3-9404-f7cfa99d17cd": "2"
}
}
}
But I’m still not sure how well this will work for IC components.