# Netlist names in labels/tags? **URL:** \ **Category:** Help\ **Created:** [August 17, 2024, 7:18am UTC](https://librepcb.discourse.group/t/netlist-names-in-labels-tags/784 "2024-08-17T07:18:39Z")\ **Posts on this page:** 20\ **Page:** 1
**Author:** ![crabfoam](https://yyz2.discourse-cdn.com/free1/user_avatar/librepcb.discourse.group/crabfoam/32/600_2.png) [@crabfoam](https://librepcb.discourse.group/u/crabfoam)\ **Post date:** [August 17, 2024, 7:18am UTC](https://librepcb.discourse.group/t/netlist-names-in-labels-tags/784/1 "2024-08-17T07:18:39Z")
I looked in the docs but didn’t see this. Is there a way to do Eagle / KiCad style net names? See the image. ![image](https://global.discourse-cdn.com/free1/uploads/librepcb1/original/1X/43a714cbf83db5616f8a06a601e433280d1d0783.png) ---
**Author:** ![crabfoam](https://yyz2.discourse-cdn.com/free1/user_avatar/librepcb.discourse.group/crabfoam/32/600_2.png) [@crabfoam](https://librepcb.discourse.group/u/crabfoam)\ **Post date:** [August 17, 2024, 7:19am UTC](https://librepcb.discourse.group/t/netlist-names-in-labels-tags/784/2 "2024-08-17T07:19:12Z")
this is what im able to do in LibrePCB ![image](https://global.discourse-cdn.com/free1/uploads/librepcb1/original/1X/0376b775a1b2d39a118cbce85b77fc5ef1791ed7.png) ---
**Author:** ![ubruhin](https://avatars.discourse-cdn.com/v4/letter/u/c89c15/32.png) [@ubruhin](https://librepcb.discourse.group/u/ubruhin)\ **Post date:** [August 17, 2024, 8:34am UTC](https://librepcb.discourse.group/t/netlist-names-in-labels-tags/784/3 "2024-08-17T08:34:16Z")
Hi, This does not exist in LibrePCB. To be honest, IMO it is confusing and thus not necessary to have two different styles of netlabels when they actually do the same thing. Or what would be the advantage of the Eagle style labels? Generally I just recommend to place the labels _above_ the lines, not next to them: ![image](https://global.discourse-cdn.com/free1/uploads/librepcb1/original/1X/7d73e8384a6977faa172b2d0ce5b74615e92a32f.png) (and theoretically it is even possible to draw your own style of netlabels, but this has several disadvantages so I don’t recommend that…) ---
**Author:** ![crabfoam](https://yyz2.discourse-cdn.com/free1/user_avatar/librepcb.discourse.group/crabfoam/32/600_2.png) [@crabfoam](https://librepcb.discourse.group/u/crabfoam)\ **Post date:** [August 17, 2024, 7:58pm UTC](https://librepcb.discourse.group/t/netlist-names-in-labels-tags/784/4 "2024-08-17T19:58:15Z")
Thanks for the response Urban! (this is Parker!). We use it to help differentiate between notes about the signal verse actual net names. Usually to indicate that the signal / net goes to another page of the schematic or somewhere else. Which does bring up a good use case for such labeling that Eagle or KiCad don’t do. Having a way to show what other pages of the schematic the signal is on. Automotive diagrams do this but I haven’t seen an EDA tool do this by default. Side note: The Eagle library importer is amazing! ---
**Author:** ![ubruhin](https://avatars.discourse-cdn.com/v4/letter/u/c89c15/32.png) [@ubruhin](https://librepcb.discourse.group/u/ubruhin)\ **Post date:** [August 17, 2024, 9:15pm UTC](https://librepcb.discourse.group/t/netlist-names-in-labels-tags/784/5 "2024-08-17T21:15:53Z")
Ah, hi Parker, nice to see you here! Hmm alright, so if I understand correctly, you don’t necessarily put the actual net name into this label? In that case theoretically you could create a custom library element for that, though it would not adjust dynamically to the text length and is not so convenient to use. I’m really not sure if it makes sense to make this a built-in feature, maybe it is more a thing of personal habits 🤔 > [@crabfoam](#): > > Which does bring up a good use case for such labeling that Eagle or KiCad don’t do. Having a way to show what other pages of the schematic the signal is on. Automotive diagrams do this but I haven’t seen an EDA tool do this by default. That’s indeed something interesting. I already got this question from people in the machine industry because the tools for drawing wiring diagrams for control cabinets also generate these cross-references. I didn’t know this is also done in the automotive sector. Maybe this would be worth implementing. > [@crabfoam](#): > > Side note: The Eagle library importer is amazing! Thanks, glad you like it 😃 ---
**Author:** ![crabfoam](https://yyz2.discourse-cdn.com/free1/user_avatar/librepcb.discourse.group/crabfoam/32/600_2.png) [@crabfoam](https://librepcb.discourse.group/u/crabfoam)\ **Post date:** [August 17, 2024, 9:48pm UTC](https://librepcb.discourse.group/t/netlist-names-in-labels-tags/784/6 "2024-08-17T21:48:10Z")
We do put the net list label in the tag/label. Its a way to tell the difference to a net note (which is just floating text next to a net) verse the actual net name. I can work around it if required. Is there a attribute for a component that can auto be populated depending on the net the pin is attached to? Similar to your first idea of a library element. Going back and manually adding them wouldn’t be the end of the world either 🙂 Side Note: The “x” part of the current net text does look like its disconnected and not really part of another section of the schematic. Maybe that is why its bugging me. ---
**Author:** ![ubruhin](https://avatars.discourse-cdn.com/v4/letter/u/c89c15/32.png) [@ubruhin](https://librepcb.discourse.group/u/ubruhin)\ **Post date:** [August 17, 2024, 10:22pm UTC](https://librepcb.discourse.group/t/netlist-names-in-labels-tags/784/7 "2024-08-17T22:22:11Z")
> [@crabfoam](#): > > Is there a attribute for a component that can auto be populated depending on the net the pin is attached to? There are two mechanisms which could be useful here. The first one is that pin labels can be configured to display the name of the connected net instead of the component signal name. The corresponding dialog is in the component editor: ![image](https://global.discourse-cdn.com/free1/uploads/librepcb1/original/1X/7eb2e2fa8e6605e59481f8aaff1b745d1acf82b3.png) However, note that this will only _display_ the name of the connected net, but it does not allow you to _rename_ the net through this label. Another way is the supply symbols approach. You might take a look at the “Supply VCC” component in the base library: ![image](https://global.discourse-cdn.com/free1/uploads/librepcb1/original/1X/548be5fab2a8fdf97a609f9a3a7a4cf76d0e4234.png) This basically works the other way around. You set a net name as the VALUE of a component. This value then gets displayed on the schematic because of the `{{VALUE}}` text. In addition, the “forced net” config will propagate this name to the net connected to it. So the net name is enforced by the component, not by the net (though currently renaming works only in disconnected state, this will be fixed some day). I think both ways are not ideal for your use-case but you might still want to try it. Also keep in mind that both ways will suppress the “less than two pins in net” ERC warning as the label’s pin is considered as a real component pin. ---
**Author:** ![crabfoam](https://yyz2.discourse-cdn.com/free1/user_avatar/librepcb.discourse.group/crabfoam/32/600_2.png) [@crabfoam](https://librepcb.discourse.group/u/crabfoam)\ **Post date:** [August 18, 2024, 12:34am UTC](https://librepcb.discourse.group/t/netlist-names-in-labels-tags/784/8 "2024-08-18T00:34:16Z")
Thanks! This helps me out a bunch and gets me to what we need. This is a bit off topic for this thread but is there a time line for a feature like the Eagle “paintroller” tool? Basically allows you to copy only specific attributes and then pastes them on other elements? ---
**Author:** ![crabfoam](https://yyz2.discourse-cdn.com/free1/user_avatar/librepcb.discourse.group/crabfoam/32/600_2.png) [@crabfoam](https://librepcb.discourse.group/u/crabfoam)\ **Post date:** [August 18, 2024, 1:23am UTC](https://librepcb.discourse.group/t/netlist-names-in-labels-tags/784/9 "2024-08-18T01:23:30Z")
Also, what is the best way to go about having pad numbers on the symbol? ![image](https://global.discourse-cdn.com/free1/uploads/librepcb1/original/1X/686b31ca95b5eebb4376c5df4a9c52e240ad8a30.png) ---
**Author:** ![crabfoam](https://yyz2.discourse-cdn.com/free1/user_avatar/librepcb.discourse.group/crabfoam/32/600_2.png) [@crabfoam](https://librepcb.discourse.group/u/crabfoam)\ **Post date:** [August 18, 2024, 1:24am UTC](https://librepcb.discourse.group/t/netlist-names-in-labels-tags/784/10 "2024-08-18T01:24:58Z")
![image](https://global.discourse-cdn.com/free1/uploads/librepcb1/original/1X/fa5c4be95c2ab4e723773bc093b60af5d92852a7.png) ---
**Author:** ![ubruhin](https://avatars.discourse-cdn.com/v4/letter/u/c89c15/32.png) [@ubruhin](https://librepcb.discourse.group/u/ubruhin)\ **Post date:** [August 18, 2024, 5:57am UTC](https://librepcb.discourse.group/t/netlist-names-in-labels-tags/784/11 "2024-08-18T05:57:30Z")
> [@crabfoam](#): > > This is a bit off topic for this thread but is there a time line for a feature like the Eagle “paintroller” tool? Basically allows you to copy only specific attributes and then pastes them on other elements? It’s already implemented for the footprint editor, but not released yet. For the other editors there’s no time line yet (feel free to open an issue on GitHub to make us keeping it in mind). > [@crabfoam](#): > > Also, what is the best way to go about having pad numbers on the symbol? They will appear automatically once you place this component on the board. Without placing it, the schematic editor doesn’t know yet what footprint is chosen (due to an underlying concept different to Eagle). ---
**Author:** ![crabfoam](https://yyz2.discourse-cdn.com/free1/user_avatar/librepcb.discourse.group/crabfoam/32/600_2.png) [@crabfoam](https://librepcb.discourse.group/u/crabfoam)\ **Post date:** [August 19, 2024, 12:34am UTC](https://librepcb.discourse.group/t/netlist-names-in-labels-tags/784/12 "2024-08-19T00:34:54Z")
> [@ubruhin](#): > > They will appear automatically once you place this component on the board. Without placing it, the schematic editor doesn’t know yet what footprint is chosen (due to an underlying concept different to Eagle). Got it! Just started layout on this project. In the Layout Editor, is there a miter tool or is only while drawing the traces? ---
**Author:** ![crabfoam](https://yyz2.discourse-cdn.com/free1/user_avatar/librepcb.discourse.group/crabfoam/32/600_2.png) [@crabfoam](https://librepcb.discourse.group/u/crabfoam)\ **Post date:** [August 19, 2024, 1:06am UTC](https://librepcb.discourse.group/t/netlist-names-in-labels-tags/784/13 "2024-08-19T01:06:57Z")
BTW layout is going well. Not having a miter tool makes it a bit interesting to fan stuff out. ![image](https://global.discourse-cdn.com/free1/uploads/librepcb1/original/1X/1357ff35a1050b46070258444ac516853057ba3f.jpeg) ---
**Author:** ![ubruhin](https://avatars.discourse-cdn.com/v4/letter/u/c89c15/32.png) [@ubruhin](https://librepcb.discourse.group/u/ubruhin)\ **Post date:** [August 19, 2024, 3:25pm UTC](https://librepcb.discourse.group/t/netlist-names-in-labels-tags/784/14 "2024-08-19T15:25:48Z")
Yeah the board editor is generally quite simple so far, not many convenience tools available. But such things will be added step by step 🙂 ---
**Author:** ![crabfoam](https://yyz2.discourse-cdn.com/free1/user_avatar/librepcb.discourse.group/crabfoam/32/600_2.png) [@crabfoam](https://librepcb.discourse.group/u/crabfoam)\ **Post date:** [August 20, 2024, 4:23pm UTC](https://librepcb.discourse.group/t/netlist-names-in-labels-tags/784/15 "2024-08-20T16:23:32Z")
I figured as much. ![image](https://global.discourse-cdn.com/free1/uploads/librepcb1/original/1X/23b85f0a205559b95dc66e6b86378b300b73c879.jpeg) Definitely see the potential. Will be finishing up this PCB design this week. I am impressed by the stability of the software. Zero problems I have run across which is a far cry from Eagle and KiCad… and Altium 😃 ---
**Author:** ![ubruhin](https://avatars.discourse-cdn.com/v4/letter/u/c89c15/32.png) [@ubruhin](https://librepcb.discourse.group/u/ubruhin)\ **Post date:** [August 20, 2024, 10:06pm UTC](https://librepcb.discourse.group/t/netlist-names-in-labels-tags/784/16 "2024-08-20T22:06:53Z")
Glad to hear that you are getting on 😊 Just one thing irritates me a bit: What are J3 and J4 exactly? They look like THT pads but with a very weird shape. Rectangular holes cannot be manufactured. Are there any intersections of custom pad outlines? Didn’t the package editor show any warnings about these pads? ---
**Author:** ![crabfoam](https://yyz2.discourse-cdn.com/free1/user_avatar/librepcb.discourse.group/crabfoam/32/600_2.png) [@crabfoam](https://librepcb.discourse.group/u/crabfoam)\ **Post date:** [August 21, 2024, 3:17pm UTC](https://librepcb.discourse.group/t/netlist-names-in-labels-tags/784/17 "2024-08-21T15:17:16Z")
> [@ubruhin](#): > > Just one thing irritates me a bit: What are J3 and J4 exactly? They look like THT pads but with a very weird shape. Rectangular holes cannot be manufactured. Are there any intersections of custom pad outlines? Didn’t the package editor show any warnings about these pads? Yes it is throwing an error for that part. ![image](https://global.discourse-cdn.com/free1/uploads/librepcb1/original/1X/baf1250fb23c8c523eeaa63e48be579dbc284b46.png) The part is a large threaded boss for attaching high current cable lugs to. Part number: B4A-PCB-RLM. [IHI - THT - B4A-PCB-RLM-KIT Ring Lug Mount Block](https://lugsdirect.com/B4A-PCB-2RLM-KIT.html) ![image](https://global.discourse-cdn.com/free1/uploads/librepcb1/original/1X/67a0a78db1ea9f8120a052824e21fb808afd588a.png) Datasheet for the mechanical footprint. [https://lugsdirect.com/PDF\_Webprint/B4A-PCB(-45)-CUTOUT-LAYOUT-FOOTPRINT.pdf](https://lugsdirect.com/PDF_Webprint/B4A-PCB(-45)-CUTOUT-LAYOUT-FOOTPRINT.pdf) Here is the library i have been building up if you want to take a look: [https://github.com/LonghornEngineer/LHE-LibrePCB-Part](https://github.com/LonghornEngineer/LHE-LibrePCB-Part) Is there a better way to design this in Libre? I am really excited that the pad editor supports plated slots from the get go, no silly workarounds! 😃 ---
**Author:** ![crabfoam](https://yyz2.discourse-cdn.com/free1/user_avatar/librepcb.discourse.group/crabfoam/32/600_2.png) [@crabfoam](https://librepcb.discourse.group/u/crabfoam)\ **Post date:** [August 21, 2024, 3:24pm UTC](https://librepcb.discourse.group/t/netlist-names-in-labels-tags/784/18 "2024-08-21T15:24:56Z")
Here is the pad settings: ![image](https://global.discourse-cdn.com/free1/uploads/librepcb1/original/1X/3fd7ca26b60e0be699406c0a75f21649a5520353.png) ![image](https://global.discourse-cdn.com/free1/uploads/librepcb1/original/1X/945a5a04838038cebc55365fbfed24f048e7982a.png) ---
**Author:** ![ubruhin](https://avatars.discourse-cdn.com/v4/letter/u/c89c15/32.png) [@ubruhin](https://librepcb.discourse.group/u/ubruhin)\ **Post date:** [August 21, 2024, 3:25pm UTC](https://librepcb.discourse.group/t/netlist-names-in-labels-tags/784/19 "2024-08-21T15:25:15Z")
Alright, I think you misread the drawing in the datasheet (it took me a while too!) 🙈 The pad outline should be larger than the slot: ![image](https://global.discourse-cdn.com/free1/uploads/librepcb1/original/1X/4f0a656a71ba560d266f4744146645614c0c72e4.png) And I recommend to always read the messages in the library editor 😃 The “hole outside copper of pad” error states exactly what is wrong with that pad. ---
**Author:** ![crabfoam](https://yyz2.discourse-cdn.com/free1/user_avatar/librepcb.discourse.group/crabfoam/32/600_2.png) [@crabfoam](https://librepcb.discourse.group/u/crabfoam)\ **Post date:** [August 21, 2024, 3:50pm UTC](https://librepcb.discourse.group/t/netlist-names-in-labels-tags/784/20 "2024-08-21T15:50:15Z")
I must have missed that! Yeah looks like I took the soldermask opening as the copper pad! Thanks for catching that. TBH I thought the route just extended past the pad.