# Via in PAD

**URL:** <https://librepcb.discourse.group/t/via-in-pad/963>\
**Category:** Help\
**Created:** [October 21, 2025, 8:05pm UTC](https://librepcb.discourse.group/t/via-in-pad/963 "2025-10-21T20:05:15Z")\
**Posts on this page:** 4\
**Page:** 1

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**Author:** ![giancarlo64](https://yyz2.discourse-cdn.com/free1/user_avatar/librepcb.discourse.group/giancarlo64/32/296_2.png) [@giancarlo64](https://librepcb.discourse.group/u/giancarlo64)\
**Post date:** [October 21, 2025, 8:05pm UTC](https://librepcb.discourse.group/t/via-in-pad/963/1 "2025-10-21T20:05:15Z")

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I have a pad that is on the top and on the bottom side and in the PCB I would like to connect the both sides with a via. If I connect the pads using a via outside the pads (with trace) is ok but if I put the via directly on the pads the DRC still tell me that the 2 pads are not connected. Why?

 ![immagine](https://global.discourse-cdn.com/free1/uploads/librepcb1/original/1X/1e7b597b97ced39d255a5290463eb003e0ba77b0.png)

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**Author:** ![ubruhin](https://avatars.discourse-cdn.com/v4/letter/u/c89c15/32.png) [@ubruhin](https://librepcb.discourse.group/u/ubruhin)\
**Post date:** [October 21, 2025, 9:08pm UTC](https://librepcb.discourse.group/t/via-in-pad/963/2 "2025-10-21T21:08:03Z")

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Hmm that is an edge case which is not properly detected indeed. For performance reasons, pads and vias are only considered connected if a trace attaches to their center point. Of course the pads are actually connected in your screenshot, the DRC just isn’t able to detect it. To get rid of the warning, traces need to be added to connect the via to the pad.

I agree it is not ideal, maybe we can improve that some day.

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<div class="post-metadata">

**Author:** ![giancarlo64](https://yyz2.discourse-cdn.com/free1/user_avatar/librepcb.discourse.group/giancarlo64/32/296_2.png) [@giancarlo64](https://librepcb.discourse.group/u/giancarlo64)\
**Post date:** [October 22, 2025, 8:00pm UTC](https://librepcb.discourse.group/t/via-in-pad/963/3 "2025-10-22T20:00:04Z")

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Hi ubruhin,

I get an error missing connection.

 ![immagine](https://global.discourse-cdn.com/free1/uploads/librepcb1/original/1X/4192f706b8535e108e5326022b258d4ab07e87de.png)

Is for the same reason?

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<div class="post-metadata">

**Author:** ![ubruhin](https://avatars.discourse-cdn.com/v4/letter/u/c89c15/32.png) [@ubruhin](https://librepcb.discourse.group/u/ubruhin)\
**Post date:** [October 22, 2025, 8:16pm UTC](https://librepcb.discourse.group/t/via-in-pad/963/4 "2025-10-22T20:16:38Z")

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Yes same reason, there is no trace attached to the vias.

For this example actually I would recommend to draw a plane instead of “painting” with traces. With planes, the airwires should disappear and it is much cleaner IMHO.