Hi,
I’m a relatively new user to LibrePCB and really like the project as it is really intuitive! My last designs worked as expected, but the current design has a new “part” I’ve not yet used and not found in the forum yet: a PCB antenna.
Concretely I want to implement the Inverted F-Antenna presented by TI in DN007. As one can see in figure 1, the antenna has a 50Ω feed point and a connection to GND. Therefore this antenna could be considered some kind of special GND-connection and manually drawn in the layout, but this would not really be the truth: it is a “component”, just not some component you buy or solder to the board. Therefore I want to create a component for this antenna, which can be assigned to the existing dipole antenna symbol (added in LibrePCB-Libraries/LibrePCB_Base.lplib#142).
But I’m lost on how to draw the “footprint” of the PCB antenna, because it is just a specially formed copper area with two special connections, but nothing to solder onto. Of course I can remove the stop mask and solder paste, but then LibrePCB warns me “ATTENTION: This library element contains serious errors”, likely caused by the DRC error “Solder resist on pad ‘ANT’ in ‘default’”.
Is there a precedence for this kind of footprint? Is this the recommended way of implementing a PCB-antenna or am I on the wrong track?
Thank you in advance!
Hi,
Honestly I never created a PCB antenna so far. But generally I’d probably do it that way:
- Draw the antenna itself as a filled copper polygon with width=0 (you may import the DXF from TI)
- Add 2 pads to the connection points (GND + feed point), overlapping the copper polygon
- Disable solder mask and solder paste on those pads
- Add a zone to disable plane filling in the antenna area
- Set the packages assembly type to None (in the metadata tab), since this is not a real device
- Approve the “suspicious pad type” warnings (if any) in the library check panel
I think that should work, but probably you will still get DRC errors later due to the “short circuit” that copper polygon creates. At the moment, this is unavoidable, so you have to approve those errors. You may also need to play around with the exact dimensions of the polygon, the zone and the pads. I think the GND pad needs to be partially outside of the zone to allow planes to connect to it. And the copper polygon should probably be fully inside the zone, to avoid it to overlap with the GND plane, which may cause additional DRC errors.
Let me know if that doesn’t work.
Thank you for your quick reply!
I’ve followed your suggestion on drawing the antenna (the only difference is that I used multiple rectangles instead of a single polygon, but this could be changed). I’ve hidden the corresponding package check warnings:
Unfortunately and as you imagined, the DRC on the board using this antenna reports multiple errors for having the polygons to close together, which is true from the point of view of LibrePCB: the GND-“pads” are too close to unassigned copper, the antenna-“pad” as well and there is a short circuit between GND and ANT. That is something I can work with, but I would not publish that antenna, because it is a bad user experience for anyone not knowing about this caveats.
But, thank you again, this solves my direct issue.
Potential changes to LibrePCB
I want to suggest some potential improvements in LibrePCB to resolve those issues.
- add a SMD-pad function “connection only”, which is a pad without solder paste or stop mask and only intended to connect the footprint up to the circuit. This would hide the package check errors associated with it.
- add a way to “connect” the polygons to the pads so that DRC errors are suppressed there. (but I’m unsure on how this could work internally and how this would be exposed to the user, an idea is sketched below)
- (optional) add a packages assembly type “PCB structure (excluded from BOM/PnP)”, which behaves similarly to “None”, but warns if
- solder paste is used
- stop mask is used
With those changes, one could create new “PCB-structures” as packages without any error except for the short between ANT and GND. This could be solved with a “don’t report a DRC-issue here”-area. The user can draw that area over the connection points of the polygons and other polygons and the pads. This is obviously a very dangerous thing to support, as it hides potential manufacturing issues.
Let me know, what you think about that 
Thanks for the feedback.
Note that it is totally fine to get package check errors on unusual package types. There exist tons of edge-cases where we have to do “strange” things in the package. Covering all of those cases would make LibrePCB way too complex for very little benefit. The package check errors are just a reminder when something looks suspicious, but if that is intended, it is totally fine to just suppress those warnings. That is how this feature is intended to be used.
But when it comes to the DRC, I agree an antenna package shall not raise any warning since this is bad user experience every time an antenna is used. Maybe the existing Zone feature could be used to suppress copper clearance/shorts errors in that area 
It may also solve the same problem we have for net-tie footprints. Anyway, I will add this to the v3.0 milestone.
A connection-only pad function might also make sense. Not because of user experience, but because of the Gerber export. If LibrePCB knows that a pad is actually not an exposed pad, it should not export it to Gerbers as a pad object. Though probably in real life this doesn’t matter, so it might not be worth to implement anything (e.g. automated PCB testing equipment usually also consider the stop mask on top of pads, so they know anyway if a pad is not exposed).
Oh, I just have a new idea for the DRC issue: Packages already have a property for the minimum copper clearance (Support specifying per-package copper clearance value by ubruhin · Pull Request #1616 · LibrePCB/LibrePCB · GitHub). Actually the DRC could ignore any copper clearance issues within packages which have this value set to 0mm. That would probably fix the issue for antennas and net ties, and doesn’t even need to be waiting for LibrePCB 3.0 since this property exists already.
Though maybe that would be a too broad DRC suppression
