Beginner question about vias

I have noticed that the solder mask of my top layer to disappear over my big vias. I don’t want this so I ran a test. By increasing the drill size of my small vias, the solder mask disappears going from 0.5mm to 0.6mm. What is controlling this?

Ideally, I would like my vias covered but pads for devices not covered. I have two size vias: big 4.2mm and small 0.9mm. Those are the annular ring diameters. The drill sizes are 1.3mm and 0.4mm, respectively.

I am a beginner so I expect there is more to this issue. Can anyone advise me?


I’m a little confused as to why you are trying to do what you are and I wonder if you are confusing plated through holes with vias. So please for give me if I’m teaching Granny.

Yes a plated through hole is a via but the purpose is different, usually. A via connects traces or planes between different layers. They are also frequently used to provide a thermal path from an ICs ground pad through to a larger copper area to which a heat sink can be attached. A plated through hole can obviously achieve the same objective but more often than not also retains a component lead, a screw, a wire. The other distinction is that vias are covered by solder resist while plated through holes are not. I think a covered via is refired to a a tented via. Vias can be berried, i.e. hidden on inner layers, they can be blind, not go through all layers. These options are not, as far as I’m aware, possible for plated through holes.

If none of the above has helped post a simple example as a reply (a picture paints and all that).

This is a two layer board.

In the picture I have pointed to two vias, one large, one small. Both were placed during the routing of metal lines as I switched between top and bottom metal. In the resulting Gerber data the small via is covered by the typically green coating on the circuit board while the large via is not. By experiment, as soon as a via reaches > 0.5mm the coating goes away in the Gerber data. This makes possible (I think) inadvertent shorting to the via in the final product. I don’t want this. The Gerber data contains round elements over these exposed vias. I had to write a program to remove them. I believe the type of vias I am wanting are called tented vias. I understand that with large vias the tenting may have a hole in it. That’s OK in my case. I am tenting the bottom side and am protecting the exposure of the vias on the top side by elements placed on the board’s top. Thus the holes will vent and moisture will not remain corrosive in the hole.

That’s my thought process. As I said I’m a beginner and there may be many flaws in my understanding. So my question is how to handle this in LibrePCB?

Thank you for you reply. I truly appreciate the help.

This can be configured in the board editor menu item Board → Design Rules → Stop Mask Max. Via Diam. Just increase this value if you want to have larger vias covered with stopmask.

Thank you. That is what I was looking for.

After reading about tented vias I opted to tent only one side of my 2-layer board. I’m not sure this is advisable, but it’s too late, I’ve done it. I wrote a small program to do it.

Thanks again for wading through my texts.