SPICE Netlist Export

Improvement Ideas
1

Would it be possible to add a Spice export?
Just a simple text file.
This could then be read and simulated in ngSpice ngSpice
Or in any other Spice program such as PSpice, LTSpice …
In the long term, the integration of Spice could then be increased

2

Hi @wieder,

Generally I have this feature in mind but not on the roadmap yet. However, this requires us to store SPICE models for each component in the library, thus it’s much more complex than “just a simple text file”. This takes a lot of time to implement. Without SPICE models in the library, I’d expect a netlist export cannot be exported at all – please let me know if I’m wrong.

3

Spice is a very old program and you need a simulation environment like LTSpice or KiCad.
This allows you to read in and simulate the text file.
Spice models for individual components are not needed in LibrePCB.
These can be added manually later and thus read into the simulation environment.
Of course, it would be desirable to have placeholders in the components to specify the Spice models in the circuit diagram so that they appear immediately in the net list.
The Spice models are then in the same folder as the net list, for example.

4

Example of a Spice Netlist
.INCLUDE xxx.mod are the Models

  • PSpice netlist created on 19.04.2010 14:42:12 with
  • EAGLE Version 5.8.0 Copyright (c) 1988-2010 CadSoft
  • EagleNet SpiceNode
  • GND 0
  • GATE GATE
  • IN IN
  • N$1 NDLR1
  • N$2 NDLR2
  • N$3 NDLR3
  • N$4 NDLR4
  • N$5 NDLR5
  • N$6 NDLR6
  • N$11 NDLR11
  • OUT1 OUT1
  • OUT3 OUT3
  • OUT4 OUT4
  • OUT5 OUT5
  • VCC VCC

.AC DEC 10 100 10G
.INCLUDE S:/BF992.mod
.OP
.INCLUDE S:/ATF34143.mod
.INCLUDE S:/NE25139.mod
.OP
C1 VCC 0 1u
C2 OUT4 OUT5 1000n
C3 NDLR4 0 100n
C4 0 OUT1 100p
C7 GATE IN 1000n
C8 NDLR1 0 100n
C11 NDLR2 OUT3 1000n
R1 NDLR11 NDLR1 560k
R2 OUT1 VCC 10k
R3 OUT4 0 100
R5 OUT1 NDLR2 260
R6 OUT5 0 50
R7 NDLR6 NDLR4 560k
R8 NDLR4 OUT3 100Meg
R10 NDLR1 GATE 100Meg
R12 VCC NDLR5 10
V1 NDLR5 0 5V
V2 NDLR11 0 -0.15V
V3 NDLR6 0 -0.15V
V5 IN 0 -1V AC 1mV
X1 0 NDLR3 GATE GATE BF992
X2 NDLR3 OUT1 0 0 BF992
X3 VCC OUT3 OUT4 ATF34143
.PROBE
.END

5

I know SPICE, but LibrePCB can’t know what *.mod need to be exported in the netlist if the models aren’t part of our libraries. It needs a tight integration with our library concept to make this possible.

And I don’t like half-baked solutions with exporting incomplete netlists where the user has to somehow integrate models manually. It would not follow LibrePCB’s philosophy of an intuitive, easy-to-use tool with efficient workflows.