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Wrong email notification
|
|
3
|
28
|
February 11, 2026
|
|
ERC and DRC Report
|
|
4
|
45
|
February 8, 2026
|
|
Import single part library in Eagle Format
|
|
2
|
53
|
February 5, 2026
|
|
Library problems during migration to V2.0
|
|
8
|
90
|
February 5, 2026
|
|
Rev 2.0 new Library Name limited to 20 characters
|
|
1
|
36
|
February 3, 2026
|
|
Symbol grid spacing on V2
|
|
1
|
62
|
February 3, 2026
|
|
Bug: ground planes in V2
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|
1
|
61
|
February 2, 2026
|
|
Portrait monitor, Dual monitor
|
|
3
|
60
|
February 1, 2026
|
|
Help for my first design Please!
|
|
3
|
40
|
January 29, 2026
|
|
Empty MPN and Manufacturer in BOM
|
|
1
|
44
|
January 29, 2026
|
|
Device name Bill of material
|
|
2
|
27
|
January 28, 2026
|
|
How to save Project with new name?
|
|
6
|
69
|
January 27, 2026
|
|
Teardrop pad connections?
|
|
3
|
41
|
January 24, 2026
|
|
New user, 1st board pretty simple questions
|
|
11
|
146
|
January 22, 2026
|
|
What layers get printed by silk screen?
|
|
5
|
76
|
January 22, 2026
|
|
Is it possible to create panelized boards in 2.0?
|
|
1
|
35
|
January 22, 2026
|
|
Empty segment of net
|
|
3
|
40
|
January 19, 2026
|
|
Creating New Component
|
|
3
|
80
|
January 14, 2026
|
|
Delete segment of trace
|
|
3
|
38
|
January 7, 2026
|
|
Component signals assignment
|
|
5
|
50
|
January 3, 2026
|
|
Enhancement Proposal: Export to CircuiTikZ (.tex) for IEEE Publication-Quality Schematics
|
|
1
|
33
|
January 2, 2026
|
|
HX711 library element
|
|
0
|
35
|
December 17, 2025
|
|
A few questions
|
|
6
|
149
|
November 25, 2025
|
|
Dimensioning pcb drawing
|
|
4
|
104
|
November 18, 2025
|
|
Import of an EAGLE sch/brd - glitch
|
|
12
|
145
|
November 1, 2025
|
|
Success story: librePCB running on Sequoia OCLP (macOS 15.7.1)
|
|
3
|
65
|
October 29, 2025
|
|
Code signing
|
|
2
|
136
|
October 28, 2025
|
|
3D not shown
|
|
2
|
73
|
October 24, 2025
|
|
Attribute Value not updated
|
|
4
|
70
|
October 24, 2025
|
|
Via in PAD
|
|
3
|
68
|
October 22, 2025
|